Silicon Exposed

Sunday, May 8, 2016

Open Verilog flow for Silego GreenPak4 programmable logic devices

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I've written a couple of posts in the past few months but they were all for the blog at work so I figured I'm long overdue for one ...
1 comment:
Tuesday, October 27, 2015

New GPG key

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Hi everyone, I've been busy lately and haven't had a chance to post much. There will be a pretty good sized series coming up in a ...
2 comments:
Saturday, May 23, 2015

Graduating, TDR prototype, lab move, and a conference talk

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So, it's been a busy couple of months and I haven't had time to post anything. Here's a few quick updates: I successfully defe...
1 comment:
Wednesday, February 4, 2015

How to lose my business permanently

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This post is a bit different from my usual ones in that it discusses the business side of the semiconductor industry, not the technical side...
2 comments:
Tuesday, January 20, 2015

TDR updates

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A few months ago, I wrote about a project I had been thinking of for a while but not had time to work on: a time-domain reflectometer (TDR...
Thursday, January 15, 2015

GERALD microscope control system

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While my optical microscopes are capable of sufficient resolution for imaging larger-process ICs, taking massive die images ( this one , fo...
1 comment:

FPGA cluster updates

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Although the "raised floor" design for my FPGA cluster looked cool, it really didn't scale. My entire desk was full, there wa...
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Andrew Zonenberg
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