Desktop raised floor

It's been a while since I've posted about a project I've done rather than a tool or some of my reversing work. This one is purely mechanical too!

First, a little background. I have a lot of FPGA/CPLD/MCU dev boards on my desk. By "a lot" I don't mean two or three... more like 20. Powering this much hardware presents some interesting problems. I don't have that many USB ports (and many of them need more power than USB can provide). Wallwarts are another obvious solution, but I don't have enough outlets or wallwarts to power 20 boards either!

I made three bar-shaped USB hubs with male mini-B ports, to plug into small development boards backplane-style. This helped a bit, but as my collection of boards grew the situation got worse.

By last May, my desk looked something like this:

My desk full of cables

Despite extensive efforts to manage the cable disaster with split tubing, there was still a giant octopus. Worse yet, my power strips were full and half of my boards didn't even have power.

The first step was to replace the loose boards with a datacenter-style "raised floor". I bought a 2x3 foot sheet of clear blue acrylic from McMaster-Carr, carefully floorplanned where all of the boards would go, and then drilled holes for each board's mounting standoffs.

Drilling holes

This operation had to be done out on the kitchen table because my office was too small to work comfortably in.

Mounting USB hubs

I mounted all of the USB hubs to the underside of the board in order to save space on top for dev boards and things I was likely to need to probe. While this seemed a good idea at first, reaching underneath them to run cables was a little tricky. After finishing the build I replaced the legs with ones several inches longer to provide the necessary hand clearance.

Before running cables, I attached all of the boards and brought it back to my desk to test the fit.

The apparatus on my desk

The "hostnames" on labels below each board are used as node names for my batch scheduler and unit test framework (more on that in a future post). In addition, those boards with Ethernet interfaces are assigned a constant IP address by my DHCP server, recorded in DNS with that hostname so I can write test cases using hostnames instead of raw IP addresses.

In an effort to reduce cable mess, I made custom cut-to-size USB cables out of cat5 cable and soldered on USB plugs. This was a very slow and laborious process because the connectors tended to melt very easily no matter what temperature I ran the iron at. BGA is no problem for me but these connectors gave me a hard time; I had yields somewhere around 60-70% even after rework. The rest of the time the connectors were melted beyond repair.

Despite the pain, I think the results were worth it. I was a little worried about signal quality as USB is supposed to be 90 ohm Zdiff and cat5e is 100, but I've noticed no problems. I did try to find 90 ohm cables but had trouble locating any.

Custom USB cables

After running all of the cables I could, a few of the boards were still unpowered and there were wallwarts everywhere, but the data wiring was a bit neater. Definitely a step in the right direction, but more work was needed.

After initial deployment

After taking that picture, I replaced most of the red electrical tape with zip ties and stick-on mount points. This made the setup a lot neater but I don't have any photos of that handy.

In order to tidy it up properly, I needed to tackle the power problem. My solution to that is a bit of a long story so I'll save that for next post :)

BGA process notes

I've gotten a lot of requests recently to share some details on my BGA assembly process, so without further ado here it is!

The board in this example is a test vehicle with an 11x11 0.8mm XBGA footprint on it, being mounted with a PIC32MX engineering sample chip. This is the same board I used in my 0201 process test.

I deliberately put several unfilled vias in the pads to demonstrate why this is a bad idea. Keep reading for details!

0.8mm XBGA test vehicle. Black marker lines highlight the row of balls that will be used for the cross section.

Since I don't have in-house stencil capabilities and haven't gotten around to ordering professionally made ones, I do all of my BGAs with flux only. My preferred flux for this purpose is ChipQuik SMD291NL no-clean rosin tack flux.

BGA pads covered in flux

The next step is to position the BGA on top of the footprint. Well-made footprints (such as the 256-FTBGA that I use on most of my FPGA boards) have the silkscreen outline slightly larger than the chip. Unfortunately this one is the same size as the chip so it was very difficult to align properly. I tried my best but it was still a little off.

BGA on footprint

I then ran the board through the standard reflow profile in my toaster oven. It's a cheap Proctor-Silex oven purchased at WalMart for something like $25. There is no thermocouple or feedback circuit in it (I have a 120VAC rated relay and a thermocouple but have not hooked it up yet.)

• Set to 90C for 3 minutes to preheat
• Set to 150C for 1 minute for thermal soak.
• Set to 210C for 1 minute for reflow. This results in a Tal of about 15 seconds.
• Turn off oven, open door, and cool to ambient with room air

Note that these numbers are not intended to describe the actual temperatures reached by the board or the oven - they're just the numbers on the dial of my specific oven. I know for a fact that the peak temperature reached at the 210C setting is in excess of 220C because that's the melting point of SAC305 solder.

I've also heard of people using oven thermometers to calibrate their reflow ovens. One word of caution for those doing this - if your sensor has a significantly higher thermal mass than your board (such as a big metal oven thermometer) its temperature will lag behind that of the less-massive PCB by a significant amount. I know of at least one hobbyist who reached the thermal decomposition point of FR4 Tg170 (somewhere around 300C) when his thermometer showed only 260!

The best way to tell when reflow is complete on an un-calibrated oven like mine is to watch the solder melt. My paste changes from a glossy gray (full of volatile flux compounds) to matte gray (once most of the flux has boiled off) to shiny silver (after the solder melts); BGA balls turn from a dull metallic color to shiny silver at melting; the chip also sinks slightly as the balls flatten from the weight of the IC. This YouTube video (not from my lab) shows what a properly reflowing BGA looks like.

The test vehicle in the oven. Note scrap-grade 4-inch silicon wafer being used as "cookie sheet".

Since this was a test board with no actual circuitry on it, the next step was to prepare to cross-section it and look at how well the joints turned out.

Although the flux I used is no-clean (and I normally leave it in place on most of my boards) cross sections look nicer if there isn't *too* much flux in the way. Since I don't have an ultrasonic cleaner yet (I do plan to buy one in the near future) I just let it soak in a beaker of 70% isopropyl alcohol for a few minutes, shook around a bit, and wiped it dry.

PCB sitting in beaker of IPA in my fume hood. Although IPA isn't particularly dangerous as solvents go, I have a general policy of keeping all open solvent containers in the hood whenever possible.

Once the board was dry I cut it in half between the black lines with a Dremel and a cut-off wheel. My ShopVac-based dust control system works reasonably well, but I want to get a HEPA vac for this in the future.

After the rough cut I polished with 1200 grit sandpaper and wiped away the dust with a wet cloth. Upon looking under the microscope I saw that the failure I was hoping to demonstrate had indeed occurred - one of the balls had been sucked down into an uncapped via by capillary action, resulting in a complete lack of electrical contact. The ball at far right had been partially sucked into the via but the solder mask dam was big enough to keep it from going in all the way.

Cross section of PCB and BGA. Note solder-filled via in center and missing ball. The far-right via annular ring seems to have snagged on something during the cutting process and been ripped up off the board.

Looking to one side of the board it was clear that the balls without vias under them had reflowed properly and were reasonably well aligned.

The black material between the balls is not underfill, it's a paste-like material made of residual flux, FR4/molding compound dust, and little slivers of copper that were ground off by the sanding process. It looks like my defluxing process didn't work as well as I had hoped; I'm going to need ultrasound to do the job properly.

One very interesting and unexpected result was visible in this cross section - the next row of vias were visible through the FR4 laminate.

Three well-reflowed balls. Note vias in next row visible through laminate.

Before closing up the lab for the night I decided to take one last picture to show what an ENIG-finished via looks like. Since this was a higher magnification image I followed the sandpaper polish with 3μm diamond paste to get a better finish.

The layers visible in this image from bottom to top are FR4 (grayish), 1oz/35μm copper foil(copper) and what looks like about 10μm of nickel (yellow-gray).  The gold plating is too thin to see at this magnification.

Cross section of ENIG-finished via.

The final frontier - 01005 passives

Once I managed to assemble a test vehicle full of 0201 passives, I started to wonder if I could manage to go any smaller with hand assembly. The final milestone was 01005, the smallest size passive component in mass production.

Not being one to duck out of a challenge, I bought a tape of 20kΩ resistors and began designing a test vehicle. The board consists of four identical arrays of footprints; each array contains eight paralleled resistors with a test point on each side. If you do the math this works out to 2.5kΩ across the entire array if all joints are good. Significantly higher or lower would mean one of them was an open or short.

The first problem (which I had anticipated ahead of time) was that my existing tweezers were simply too large to pick up a component of this size.

01005 passive on 0.5mm TQFP footprint, seen next to my normal tweezers

I decided to buy a set of Dumont-brand Swiss watchmaker's tweezers with 50 micron points, which are significantly smaller than my old ones (but much more fragile - I've already slightly bent one of the tips despite being quite careful!)

The same component next to my new tweezers

Paste application used the same tried-and-true method as my earlier 0201 test - squirting a tiny dab of paste onto a microscope slide and using a scalpel blade as a "putty knife". In the interests of time I only hooked up a single column.

To give a better idea of how small the components (and the entire board) is, I put an 8-pin SOIC on it.

Solder paste applied to the second column with SOIC-8 for scale. The exposed copper rings around the probe pads are the result of an error in the solder mask pattern.

Paste volume was highly varied, suggesting I need to work on either better control of the scalpel technique or replacing it entirely.

Beginning component placement. Note heavy variability in paste volume.

After finishing component placement I took a closer look under the Olympus scope to see how things turned out.

Darkfield image of placed components before reflow. Focal plane is just above the top of the solder mask.

I ran the board through my standard reflow profile in the toaster oven and let it cool. From a quick inspection it looked pretty good - no tombstoning or obvious shorts/opens.

This was confirmed with an ohmmeter check - 2.50KΩ exactly. Looks like a complete success :)

Board post-reflow. Note probe scrub marks on test pads.

Darkfield closeup of a single component. Slight misalignment is visible on the one at the top edge, but electrical test passes.

Assembled board seen next to an 14-pin PDIP for scale.

It was a rather labor intensive process but the end result was a complete success. While I certainly am not about to go and use all 01005 components on my future boards, if it becomes necessary to stick something in a tight place it's good to know my process can handle it.

Fab screwups, then taming the 0201 passive

Since I've already developed a reliable process for reflowing 0402 surface mount components, as well as 1mm pitch BGA, the next logical step was 0201 passives.

I made a 1x1 inch test board with a bunch of 0201 footprints plus several other test structures (I hope to fool with homebrew filled vias at some point so I included an 0.8mm BGA with drilled-out pads on the same dummy board) on DorkbotPDX's batch order. When I eagerly opened my purple envelope late last month I was quite annoyed to discover that my soldermask pattern was completely wrong!

Soldermask bugs

The component values on the silkscreen were a screwup on my part but the fab had totally borked the mask. The correct pattern had the via fence unmasked and all of the areas around components masked.

After emailing back and forth with Laen we figured out the problem - my soldermask polygon had gone slightly outside the board outline and a bug in his panelization script resulted in the offending vertex being deleted, rather than clamped to the board outline. He offered to make me a new batch of boards at no cost.

The new boards arrived today and I inspected them briefly under the microscope. As usual they were superb quality, with near-perfect registration between layers.

Pre-assembly inspection of 0201 footprints

My first attempt at applying solder paste using a 22 gauge needle was a complete failure. There was as much paste between the pads as on them.

Somehow I don't think this will work...

I tried scraping the paste around with a scalpel blade and managed to get something halfway decent, but it still wasn't nearly as clean as I wanted. After thinking for a bit I decided to try squirting paste onto a microscope slide, then picking up a tiny blob with the blade and touching it to the component pads. This actually worked out surprisingly well!

Paste applied with scalpel blade

I wasn't expecting to get any better than this (for scale, the traces between the pads are only 150 μm wide) so the next step was to place components.

After component placement

This took a few tries but my super-fine-point tweezers were a huge help. The pitch I used seems to be about the sweet spot - pretty dense, but not so close that my tweezers bang into the next component in line while placing one.

I ran the board through my standard reflow profile in a toaster oven, then inspected.

Post-reflow inspection looks good!

Everything looked good, there were no visible shorts (confirmed by electrical testing) and all connections seemed solid and low resistance. I took a few more photos at varying angles and magnifications to verify.

Angled view of a single component. Note the size of the component in relation to the 35 μm thickness of the 1-ounce copper trace!

One of these days I need to try using stencils for paste application. In the meantime, it looks like 0201 passives are labor-intensive but definitely within reach for high-density designs.

First BGA board

(NOTE: This was originally scheduled to happen a lot earlier but the fab screwed up shipping on the boards. I only got them today.)

A while ago I decided to get serious about doing a design based on the Spartan-6 FPGA. Unfortunately all but the smallest part in the family are BGA only. They're somewhat pricey ($40ish for the XC6SLX25) so I figured it'd be a good idea to practice on something less expensive!

Quick calculations given the DorkbotPDX batch order's design rules showed that anything under 1mm pitch was not possible in a full array since a via could not fit between adjacent balls. This rules out the CPG196, CSG225, CSG324, and CSG484 packages. The remaining options are FTG256, FGG484, FGG676, and FGG900. FTG256 looked like the easiest as it had the least pins.

I did a bit of catalog browsing and determined that the cheapest FTG256 part available from Xilinx was the XC3S50A, which at $10 a pop was still a bit expensive for testing BGA soldering processes.

Eventually I settled on CPG56 packaged CoolRunner-II CPLDs as my first victim (Digikey page). CPG56 is 0.5mm pitch but is only two concentric rings, not full array.

CPG56 packaged CPLD

The next step was to design a board. I went with a simple 2-layer design that did not break out all of the balls, but seemed to offer enough IOs to be useful for casual testing.

Once the boards arrived I quickly inspected them under my microscope. They were the typical DorkbotPDX batch boards - purple LPI soldermask and ENIG finish on the pads. Some of the unbonded pads (A7-A9) appeared to have lifted off the board or underetched during manufacture. Since the pads weren't being used in the board layout this was not a problem, though it did mean the chip would be attached a bit less securely. I forgot to take a photo of this but will try to upload one soon.

I have a Proctor-Silex toaster oven I had used for reflow several times in the past but never on a BGA. There is no thermocouple or automatic temperature profile control on the oven yet (a Type-K thermocouple is inbound from Sparkfun as I write this) so I used my standard manual profile for lead-free solder, adjusting the thermostat by hand for each step:

• Heat quickly from room temperature to just below 100C
• Soak at 100C for 30-60 seconds
• Ramp up to 180C, hold for 15-30 seconds
• Ramp up to 220C, hold for 15 seconds
• Open door, wait 30 seconds, remove board

The first two attempts at soldering failed as the chip was not even close to correctly aligned. The first (pic coming soon) was so far off (about 250 μm) that none of the balls even touched the pads. Visible holes in the flux residue showed just how far off center it had been. The second was slightly better but still not usable.

One of the first two reflow attempts

On the third attempt I paid extra attention to centering the chip and it seemed to turn out well. I then hand-soldered the clock oscillator, voltage regulator, JTAG header, and the 0402 sized decoupling capacitors on the back.

When I attempted to solder the breadboard headers I realized I had used the wrong drill size and the pins didn't fit. Since the only ones I really cared about were power and ground I just soldered two wires into the holes.

Finished board, top view

Finished board, bottom view

Electrical test showed no shorts anywhere between adjacent balls. Optical inspection looked good too.

Side view of CSBGA

After hooking it up to a 3.3V power rail and a JTAG programmer, I was able to successfully program it with a simple design (divide-by-2 counter). Oscilloscope confirmed a nice 10 MHz squarewave on the output when driven by 20.